Analysis of Charge Pump Topologies for High Voltage Mobile Microphone Applications

This paper presents a novel analysis of charge pump topologies for very high voltage capacitive drive micro electro-mechanical system microphones. For the application, the size and power consumption are sought to be minimized, and a voltage gain of 36 is achieved from a 5 V supply. The analysis compares known charge pump topologies, taking into consideration on resistance of transistors and parasitic capacitances of transistors and capacitors in a 180 nm siliconon-insulator process. The analysis finds that the Pelliconi charge pump topology is optimal for generating very high bias voltages for micro electro-mechanical system microphones from a low supply voltage when the power consumption and area are limited by the application.


I. INTRODUCTION
Microphones are used in a wide array of consumer products, such as smart phones, smart watches, laptops, headsets, and tablets [1]. Today, the most widely used type of microphone is the Micro Electro-Mechanical System (MEMS) microphone, as this type of microphone may have a long range of benefits over the alternatives [2]. Multiple applications seek microphones with higher Signal-to-Noise Ratio (SNR) performance to improve or add features. One application is smart assistants, such as Amazons Alexa and Apples Siri [3], where a limitation to the user experience is how well the voice command is picked up. Distinguishing speech from noise is easier if the SNR of the microphone is high.
The dominant contribution to noise in MEMS microphones is the squeezed-film effect [1], [4], which can be reduced by increasing the distance between the backplate and the diaphragm of the microphone. However, doing this will also reduce the signal strength, unless the bias voltage is increased as the air gap is increased. Recent studies have looked into improving the SNR by increasing the air gap and using a bias of a hundred volts or more [5], [6].
A limitation to using more than a hundred volts in a MEMS microphone is the generation of the high voltage, as only a low supply voltage is available in mobile products. Furthermore, MEMS microphones can be as small as 2.5 mm × 1.6 mm × 0.9 mm (Cirrus Logic CS7331P), which leaves very little room for electronics to generate high Manuscript received 14 January, 2021; accepted 2 April, 2021. voltages from a low supply voltage. The most viable option is to go for a fully integrated solution on an Integrated Circuit (IC), as there is no room for discrete components in a MEMS microphone package. Inductors in ICs are generally unsuitable for power conversion, as integrated inductors exhibit poor performance, which leaves switched capacitor converters, such as charge pumps, as the most viable route.
A limitation to high voltage in ICs is the breakdown voltage of the process technology. This limitation can be mitigated by a type of process technology called "Silicon-On-Insulator" (SOI), which can sustain voltages of up to more than 200 V. In this work, a 180 nm SOI process with a breakdown voltage higher than 200 V is used as the targeted platform, and the device parameters to use in the analysis are extracted from the process technology.
The analysis carried out in this work has a focus on high voltage gain, small area, and low power consumption for mobile MEMS microphone applications. The specific goal is that the charge pump should be capable of reaching an output voltage of 180 V from a supply voltage of 5 V, while keeping the area less than 0.25 mm 2 and the power consumption less than 20 µW. As MEMS microphones are based on the capacitance between two plates, the only power consumption is the current leakage in the MEMS module. The current leakage is generally very small, and for a MEMS capacitor of 500 µm × 500 µm with an electric field of 2 MV/cm, the leakage was measured to be less than 1 nA [7]. Hence, the charge pump does not need to deliver significant power, as air gaps of multiple µm are common [1].
The remainder of this paper is organized as follows. Section II presents an analysis of voltage gain in charge pump topologies. In Section III, power loss analysis of selected topologies is carried out. Equivalent output resistance of selected topologies is calculated in Section IV. Settling time is investigated in Section V. Section VI provides a discussion on the two most promising topologies, and finally, the conclusions are presented in Section VII.

II. VOLTAGE SCALING OF CHARGE PUMPS
The most critical design goal for the target application is the generation of 180 V from a 5 V supply. Therefore, the first part of the analysis focuses on the voltage gain of different charge pump topologies.
Six general charge pump topologies were identified from literature, namely, the Dickson [8], the Cockcroft-Walton [9], the Pelliconi [10], Makowski/Fibonacci [11], Doubler [12], and heap [13] charge pumps. Many other topologies exist, but they are in essence just modified versions of the listed topologies, and therefore feature the same voltage gains, voltage swings, and device stresses. The six topologies are depicted in Fig. 1 and Fig. 2, where the clock signals A and B are non-overlapping. The voltage gain of all six charge pump topologies can be explained using the generic charge pump topology shown in Fig. 3(a). In one phase, the pump capacitor C pump is charged to V 1 , as depicted in Fig. 3(b). In the second phase, the capacitor bottom plate potential is lifted by V 2 and C pump is pumping charge to the output, as depicted in Fig. 3(c), with an ideal output voltage of V 1 + V 2 The generic topology can represent one stage of all topologies in Fig. 1 and Fig. 2, the only thing that changes is where V 1 and V 2 is supplied from. For example, in the Doubler topology, both V 1 and V 2 are supplied from the previous stage, and in the Dickson topology, V 1 is supplied from the previous stage and V 2 from the clock signal.    .

Topology Voltage Gain
The voltages across, respectively, capacitors and transistors/diodes of the different topologies depend in most cases on what stage of the charge pump it is. For ideal charge pumps, the voltages across the different types of devices in stage k of a topology are listed in Table II.

Topology Transistor
When parasitic capacitances are introduced in a charge pump, the voltage gain changes due to charge sharing. To properly evaluate the voltage gain of the charge pump topologies, the parasitic capacitances due to devices should be included. Hence, the parasitic capacitances of active devices and capacitors were extracted from the SOI process.
Five different parasitic capacitances were extracted for the transistors: t gate to source C gs , gate to drain C gd , drain to source C ds , source to handle wafer C sh , and drain to handle wafer C dh capacitance. For simplification, the bulk was connected to the source, which eliminates the source-to-bulk capacitance from calculations and combines the drain-tobulk and drain-to-source capacitances into the drain-tosource capacitance. In the SOI process, the bulk is on top of an insulating silicon oxide, which is on top of a layer of substrate. The layer of substrate is also called the "Handle Wafer" (HW). This layering of bulk, insulator, and substrate creates a drain to HW capacitance C dh and a source and bulk to HW capacitance C sh . The capacitances are also depicted in Fig. 4. For a HV diode, the anode to cathode capacitance C ac , anode to HW capacitance C ah , and cathode to HW capacitance C ch were extracted (see Fig. 5). The parasitic capacitances extracted for a selected range of devices are listed in Table III, together with the minimum device area. The equivalent PMOS transistors of the process have the same voltage ratings and similar parasitic capacitances. Capacitors have parasitic capacitances as well, this is depicted in Fig. 6, where the parasitic capacitance on the top plate C par,top of the capacitor may be different from the parasitic capacitance on the bottom plate C par,bot of the capacitor. For a range of capacitors available in the IC process, the parasitic capacitances were extracted. The extracted parasitic capacitances are listed in Table IV, along with the voltage rating and capacitance density of the respective capacitors. The parasitic capacitances for the capacitors are based on parasitic extraction from capacitors of 100 fF.  All transistors in the SOI process have a maximum gate to source voltage of 5.5 V, including transistors rated for a +100 V drain to source voltage. Due to this limitation on the gate-to-source voltage, the Dickson and Cockcroft-Walton topologies must be run with a supply voltage of 2.5 V or lower, or run from a 5 V supply and utilize HV diodes. For the Heap, Fibonacci, and Doubler topologies, it is necessary to use 100 V transistors to reach an output voltage of 180 V.
The voltage scaling in Table I is only correct in the ideal case. When parasitic capacitances are introduced, the voltage gain is reduced due to charge sharing. In Fig. 7, a parasitic capacitance C par is introduced on the node, where the top plate of the pumping capacitor is connected. With the parasitic capacitance present, the output voltage is given by 12 .
There is also a parasitic capacitance on the bottom plate, but, e.g., V 1 and V 2 are assumed to be ideal sources, hence the bottom plate parasitic would be connected directly to a supply, and therefore does not affect the voltage. If V 1 or V 2 are supplied from another charge pump stage, the parasitic capacitances on S 1 , S 2 , S 4 , and the bottom plate parasitic capacitances would affect the voltage gain of the supplying stage. The capacitance C par in Fig. 7 would contain the top plate parasitic capacitances of the capacitor, the parasitic capacitances of the devices used to realise S 1 and S 2 , and wiring capacitance.
Expressions of the voltage gain in different topologies, when parasitic capacitances are considered, have been derived and are shown in Table V, where α is given by where C pump,k is the effective pumping capacitance in stage k and C par,k is the combined parasitic capacitance in stage k on the top plate of the pumping capacitor.
Given a Dickson topology realised using diodes, depicted in Fig. 8, which is transitioning from phase A to B, the parasitic capacitance in stage 2, denoted C par,2 , is expressed as The pumping capacitance is Only the C ac of D 2 is included in the expression, as C ac of D 3 is in parallel with the conducting diode. Furthermore, it is assumed that the capacitance C 1 is much larger than the capacitance C ac of D 2 , such that the reduction in parasitic capacitance due to the serial connection of capacitors is negligible. In Table V, V 0 , V -1 , and V -2 are equal to V supply the supply voltage. For the Heap, Cockcroft-Walton, and Fibonacci topologies, the stacking of capacitors lowers the effective pumping capacitance, but not the parasitic capacitances. The effective pumping capacitance C pump,k for the Heap, Cockcroft-Walton, and Pelliconi topologies is listed in Table  VI, where C stage,k is the capacitance of the capacitor used in stage k. For subscript values of 0 or less, C pump,k-1 and C pump,k-2 should be omitted from the expressions. For the Dickson, Pelliconi, and Doubler topologies, C pump,k = C stage,k , as there is no stacking of capacitors.
To compare the voltage gain capability of the different topologies, the voltage gains for implementations of 0.04 mm 2 and 0.25 mm 2 were calculated using the expressions from Table V and Table VI. The 0.25 mm 2 is the target area, and the 0.04 mm 2 was used to investigate if the topologies could be implemented on less area. Devices used for the calculations were chosen from Table III and  Table IV, based on the voltage stress of each device in each stage of the charge pump, which was identified using the expressions from Table II.  The calculations of voltage gain only consider the reduced voltage gain that is due to charge sharing between pumping capacitors and parasitic capacitances. Voltage drops across diodes and transistors, the area to implement level shifters, the power required to drive level shifters, and leakage were not included in the calculations. The calculations were carried out numerically. First, the area for active devices was allocated based on the used devices and the number of stages, then the remaining area was allocated to capacitors. For each topology, the number of stages was optimized towards achieving the lowest number of stages required to reach a voltage gain of 36, or to the highest attainable voltage gain if a gain of 36 could not be reached.
For all calculated implementations, devices of sufficient voltage rating were used where necessary to save area and maximize pumping capacitance. For example, in the first stage of the Doubler topology, 5 V transistors are used, and in the last stage, 100 V transistors are used. Furthermore, for the Doubler topology, only half of the area was used to yield the area for the capacitors between stages [12]. In topologies, where capacitors are stacked, a higher voltage gain may be achieved by tapering of capacitor sizes [15], this has not been done in the calculations of this paper. Instead, each stage has been allocated an equal amount of area for pumping capacitors. A tapered Heap topology may achieve a 30 % higher voltage gain than a non-tapered Heap topology [15]. For all of the Pelliconi topology, 5 V transistors were used, and for all Cockcroft-Walton and Dickson topologies, 10 V diodes were used.
The calculated voltage gains for the charge pump implementations on a 0.04 mm 2 and 0.25 mm 2 area can be read from the plots in Fig. 9 and Fig. 10.
The Dickson, Fibonacci, Pelliconi, and Doubler topologies were in calculations, all able to reach a voltage gain of 36, both with the 0.04 mm 2 and the 0.25 mm 2 area constraint. From Fig. 9 and Fig. 10, it can be observed that the Pelliconi topology requires fewer stages than the Dickson topology when the area is constrained to 0.04 mm 2 . This is due to less parasitic capacitance in each stage and the smaller size of devices used in the Pelliconi topology, both enabled by the lower voltage stress on the transistors.
The Heap and Cockcroft-Walton topologies were not able to reach a voltage gain of 36 at the given area constraints when parasitic capacitances were included. To obtain a voltage gain of 36 with the Heap topology, the area needed to be approximately 11 mm 2 . This area could be lower if tapering was used, but even with tapering, the 0.04 mm 2 or 0.25 mm 2 implementations would not reach a voltage gain of 36. No matter how much the area was increased, the Cockcroft-Walton could not reach a voltage gain beyond approximately 14 due to the parasitic capacitances of the capacitors and diodes available in the process. If the input voltage is reduced to 2.5 V to allow the use of diodecoupled 5 V transistors, the voltage gain increases to approximately 18, but the required voltage gain to reach 180 V increases to 72.
As the Heap and Cockcroft-Walton topologies are not able to obtain a voltage gain of 36 with a supply voltage of 5 V, the two topologies are not feasible for the target application on the used platform. In the following section, a further analysis of the Dickson, Pelliconi, Fibonacci, and Doubler topologies is carried out.

III. DYNAMIC POWER LOSSES IN CHARGE PUMPS
As the target application is a capacitive load, the output power is low. At 2 nA and 180 V, the output power is only 360 nW. It is therefore very likely that the power consumption of the charge pump is dominated by switching losses to parasitic capacitances. To determine the most viable charge pump topology, the selected power losses to parasitic capacitances were estimated. Given an ideal voltage gain for each of the four topologies, the node voltages and the associated voltage swings were determined for each topology.
Switching losses were estimated using (4) 2 ,  loss clk par swing P f C V (4) where f clk is the switching frequency of the charge pump, C par is the combined parasitic capacitance connected to the node in the topology with the highest voltage swing and the most parasitic capacitance, and V swing is the voltage swing at the identified node.
For the Fibonacci and Doubler topologies, the two nodes in each charge pump with the highest voltage swing were chosen for power loss estimation. The voltage swings of the last stages of the Fibonacci are depicted in Fig. 11, and for the last stages of the Doubler, in Fig. 12, along with the nodes A and B, which represent the nodes with the highest voltage swing. The capacitor C 2 in Fig. 11 will have a potential of 111 V, thus the capacitor used for C 2 in the Fibonacci topology must be the 200 V capacitor from Table  IV, which has a very large bottom plate parasitic capacitance. For the Doubler topology, the capacitor C 3 in Fig. 12 will have a voltage of 90 V, and it must also be a 200 V capacitor.  The transistor realization of the Pelliconi topology is depicted in Fig. 13, as it can be observed that there are more than twice as many devices per stage as in the Dickson topology. However, due to the transistors having low voltage stresses, the topology can be implemented using 5 V transistors, which achieves that the Pelliconi topology has less parasitic capacitance than the Dickson topology.
For the four topologies, the parasitic capacitances were estimated by the device sizes found for the 0.04 mm 2 implementations to keep the parasitic capacitances and thereby the switching losses small. For the Doubler and Fibonacci topologies, the switching power loss was also calculated for implementations where the pumping capacitance of the last stage was reduced to 50 fF to minimize the parasitic capacitance. It was calculated that the pumps would maintain a voltage gain of at least 36.
The power losses were calculated using a 100 kHz switching frequency, and the results are listed in Table VII along with the identified voltage swings, pumping capacitance of the last stage in each pump, and the determined amount of parasitic capacitance used for power loss estimation. For the Dickson and Pelliconi topologies, C pump is the pumping capacitance used in every stage of the charge pump.  Based on the estimated switching power losses, it can be observed that the Doubler and Fibonacci topologies cannot meet the power consumption criteria set in this work. If charge recycling was to be utilized to reduce power consumption, it would require HV transistors to implement, which would likely negate the benefit due to further added parasitic capacitances. This leaves the Dickson and Pelliconi charge pump topologies as the better choices to meet the design goals of this work, and they are therefore the only two topologies investigated in the following section.

IV. SWITCH CAPACITOR CONVERTER EQUIVALENT MODEL
The analysis so far has not considered the power that is to be delivered to the load. In [16], switched capacitor converters are modelled as the circuit depicted in Fig. 14, where the output voltage V out of the converter is the voltage division of the converter ideal output voltage. The ideal output voltage is defined by the ratio of m/n in the transformer, and the voltage division is defined by R out and R load . The output voltage is expressed by where R out is the equivalent output resistance of the converter (in this work, the equivalent output resistance of the charge pump) and R load is the load resistance. Fig. 14. Switched capacitor converter model as in [16].
The load resistance for this work is 90 GΩ, as this results in 2 nA at 180 V. In [16], the equivalent output resistance is estimated by where R FSL defines the Fast Switching Limit (FSL) of the converter. R FSL is a function of the on resistance of the switches used to realise the switched capacitor converter, and how the charge is transferred in the converter. In [16], FSL is defined by   where a r j,i is a vector that defines how much charge is transferred by switches in each of the converter's phases, r i is the on resistance of the different switches, and D j is the duty cycle of each phase.
In (6), the R SSL component defines the Slow Switching Limit (SSL), and is a function of the switching frequency, capacitor size, and how the charge is transferred by the capacitors in the converter in each phase. In [16], R SSL is defined by where a j,i describe the charge transfer by capacitors, C i is the size of the various capacitors, and f clk is the switching frequency of the converter. Details on how to define a r j,i and a j,i can be found in [16].
The equivalent output resistance was calculated for 36 and 37 stage Pelliconi implementation, and for 41 and 42 stage Dickson implementation, all based on component values from a 0.04 mm 2 area restriction. The ideal voltage gain of the charge pump was based on the gain when parasitic capacitances are present. For the transistors in the Pelliconi topology, an on resistance of approximately 8 kΩ and 37 kΩ was extracted from the PDK for, respectively, minimum sized NMOS and PMOS transistors in the triode region. For the Dickson implementation, an equivalent on resistance of 8 kΩ was assumed for the diodes to be used in the calculations.
The calculated resistances and resulting output voltages for a 90 GΩ load are listed in Table VIII. From Table VIII, it can be observed that the output resistance reduces the output voltage of the 36 stage Pelliconi and the 41 stage Dickson such that they do not reach an output voltage of 180 V. For the 37 stage Pelliconi and 42 stage Dickson charge pumps, the capacitor sizes were reduced to make room for another stage on the 0.04 mm 2 . The additional stage increased the voltage gain and the equivalent output resistance, but the increase in voltage gain was higher than the increased reduction in output voltage, making it possible to reach 180 V. Even though the output resistance of the charge pump is high, the output voltage only diminishes a few percent due to the load being 90 GΩ. From the table, it can also be observed that the output resistance is dominated by the R SSL component of R out . For charge pump implementations with larger capacitors or higher switching frequency, R SSL would be lower, and so would the equivalent output resistance.
As the Dickson and Pelliconi topologies still have comparable performance, the settling time performance will be analysed in the next section.
V. SETTLING TIME Settling time for the charge pumps is also a significant parameter, as microphones often are turned on and off in mobile devices to save power. The equivalent output resistance of the converter and the capacitive load of the microphone will basically work as a capacitor charged through a resistor. The time constants and 95 % settling time were calculated for the Dickson and Pelliconi charge pumps based on a load of 10 pF and the equivalent output resistance from Table VIII. The resulting time constants and settling times are listed in Table IX. Based on the equivalent output resistance, the Dickson topology takes almost 50 % longer to reach 95 % of the maximum output voltage. Furthermore, this was based on the Dickson being implemented with switches that had an on resistance of 8 kΩ. The Dickson topology is usually realised using diode-coupled transistors or diodes, as depicted in Fig.  8. When the Dickson charge pump approaches its maximum output voltage, the voltage across the diodes or diodecoupled transistors is reduced.
When the Pelliconi and Dickson charge pumps reach 90 % of their output voltage from a 5 V supply, there is approximately 0.25 V across each transistor in the Pelliconi topology, assuming equal voltage distribution and 0.439 V across each diode in the Dickson topology. For the Pelliconi topology, the transistors will operate in the triode region, and the charge pump will have the R out listed in Table VIII. From the PDK, it was extracted that the 10 V diodes used in the Dickson topology with a voltage of 0.439 V across each conduct 34.62 pA, which is equivalent to a resistance of 12.7 GΩ.
The equivalent on resistance of 10 V diodes will dominate the equivalent output resistance of the Dickson charge pump, as 12.7 GΩ per diode results in an R FSL = 1.04 TΩ. The heavily increased output resistance of the Dickson charge pump will not only increase the time constant significantly, it will also reduce the achievable output voltage of the loaded charge pump, which is obvious given that the current through the diodes must be 2 nA to satisfy the requirement of 180 V for a 90 GΩ load.
As the Pelliconi topology already exhibits better performance than the Dickson on settling time, voltage gain per stage, and power consumption parameters, it was decided not to investigate the equivalent output resistance of the Dickson topology further in this work. In the following section, the possible ways to get around the problem of 10 V diodes are discussed.

VI. DISCUSSION
Given the estimates in Table VII and Table VIII, the Dickson and Pelliconi topologies have a comparable performance. The lower voltage stress in the Pelliconi topology enables the use of 5 V devices, which results in a lower amount of parasitic capacitance. The lower amount of parasitic capacitance results in a lower power consumption, a higher voltage gain per stage, and a lower equivalent output resistance for the Pelliconi topology than what is achieved in the Dickson topology.
When the voltage-dependent behaviour of the devices used to implement switches in the topologies is taken into consideration, it is observed that the performance of the Dickson topology is reduced significantly, while the performance of the Pelliconi topology is only reduced slightly. In the Dickson topology, the performance decreases significantly as the charge pump settles and the voltage across the diodes is reduced. The reduced voltage across diodes leads to a much higher equivalent output resistance, which affects both the time constant for settling and the achievable output voltage negatively. The supply voltage of 5 V does not allow diode-coupled transistors to be used in place of the 10 V diodes. 10 V transistors in combination with level-shifters would mitigate the voltage stress and conductivity challenges, but require extra circuitry, leading to a higher power consumption and the introduction of additional parasitic capacitance. If the supply voltage were 2.5 V instead of 5 V, the Dickson topology would be able to use diode-coupled 5 V transistors instead of 10 V diodes. This would improve the performance of the Dickson topology, as the conductivity of diode-coupled transistors in the SOI process is higher than that of the 10 V diodes when small voltages are applied. Additionally, the parasitic capacitances in the Dickson topology would become less than the parasitic capacitances in the Pelliconi topology, and thereby improve the performance of the Dickson topology.
In the calculations estimating the implementations on 0.25 mm 2 and 0.04 mm 2 , the area required for wiring and for the distance between devices were not included. If the capacitor sizes from those estimates were used for a physical implementation, the implementation would be larger than the area used for the calculations. As the estimate of a Pelliconi implementation of 0.04 mm 2 was able to reach 180 V, it should be possible to implement physically on less than the goal of 0.25 mm 2 .

VII. CONCLUSIONS
In this paper, an analysis of known charge pump topologies was carried out to determine the optimal topology for a mobile microphone application. The goal of the analysis was to determine which charge pump topology is optimal for reaching 180 V from a 5 V supply, while keeping the area of an IC implementation below 0.25 mm 2 and the power consumption below 20 µW. It was determined that the two most suitable topologies are the Dickson and Pelliconi topologies, and that the Pelliconi outperforms the Dickson topology given the devices available in the SOI process used for device parameters. The Pelliconi topology is predicted to have a significantly shorter settling time than the Dickson topology due to the devices used. Dependent on the devices available, other charge pump topologies may exhibit better performance in other applications. Finally, the estimations of the Pelliconi topology indicate that the charge pump can be implemented on a chip area of less than 0.25 mm 2 , as the 0.04 mm 2 estimations meet the output voltage and power consumption goals.

CONFLICTS OF INTEREST
The authors declare that they have no conflicts of interest.