A Lossy Capacitance Measurement Circuit Based on Analog Lock-in Detection

This paper presents a lossy capacitance measuring circuit which is based on analog lock-in detection technique. Lossy capacitance can be modelled as a pure capacitor connected in parallel with a resistor. The measurement circuit mechanism consists of an excitation signal to drive the lossy capacitance, a transimpedance amplifier to produce a voltage, and a lock-in detection circuit to extract lossy values of capacitance. The lock-in detector multiplies its input with a square wave using switches and filters out high frequencies to give a DC output that is actually in proportional to the measured values. A field programmable gate array is employed to generate direct digital synthesis based sinusoidal excitation signal to generate reference signals required for demodulation and to measure the output of lock-in detection. The phase shift between the excitation signal and reference signals is controlled accurately in digital domain. Thus, due to the phase mismatch, errors are properly reduced. Also, analog phase shifter and analog switch-driving circuits are no longer required. Three different lossy capacitors realized using discrete components are simulated and tested. The maximum relative error is 1.62 % for the resistance measurement and 6.38 % for the capacitance measurement.


I. INTRODUCTION
Capacitance measuring based sensing is an efficient method to detect many real-world parameters [1]. Capacitive sensors can be used in measurement of displacement [2], pressure [3], force [4], humidity [5], moisture [6] or liquid level [7]. Capacitances are inherently lossy [8] and they can be represented as an ideal capacitance Cx in parallel with a loss resistance Rx as shown in Fig. 1. The lossy capacitances can also be modeled as variable resistor and capacitors in parallel [9]. Cp1 and Cp2 represent stray capacitances, which arise from cables connected to the measured capacitance [10] and result from the input capacitance of the amplifier used [11]. The effect of Cp1 can be reduced by exciting the lossy capacitance with a lowimpedance input signal from terminal 1 in Fig. 1 [12]. The measuring circuit's insensitivity to Cp2 can be assured by virtually grounding terminal 2 in Fig. 1 using an operational amplifier (op-amp). The potential difference over the parasitic capacitance is maintained at zero volts [13].
Manuscript received 18 April, 2020; accepted 20 August, 2020. Driving the lossy capacitance with an AC voltage source creates a current which flows through Rx and Cx. A transimpedance amplifier (TIA) consisting of an op-amp and a feedback resistor converts this current into voltage. This voltage value contains information regarding the unknown resistance and capacitance. In order to extract capacitance and resistance values, a demodulation method called lock-in detection can be used [14]. Lock-in detection circuit gives a DC output voltage which is a function of its input signal's amplitude and the phase difference between the input and reference signal. Basically, lock-in detection rectifies its input signal and takes average of the rectified signal, and it is especially useful in the presence of noisy input signals [15]. The detection circuit comprises a multiplication unit and a low-pass filter (LPF). The multiplication unit can be realized using analog multipliers or switches. Although analog multipliers are better at being insensitive to harmonics introduced by the multiplication, they are expensive [16]. In this work, low cost analog switches are employed for the multiplication unit. Multiplication operation multiplies the input signal with +1 or -1 depending upon the positions of analog switches which are controlled by reference signals. A field programmable gate array (FPGA) can be used to provide both the driving signal and reference signals [17]. In FPGA fabric, the sinusoidal excitation input can be produced by direct digital synthesizer (DDS) method [18]. The excitation signal's amplitude and frequency can be controlled digitally using DDS which offers extra flexibility. Also, the phase shift between the driving signal and reference signals can be controlled precisely so that errors due to the phase shifts can be reduced [19]. The output of the multiplication is followed by a LPF that determines the DC level of the multiplied signal [20].
This DC output signal can be expressed as a function of unknown capacitance and resistance plus known parameters of the overall circuit. Unknown resistance and capacitor parameters can be calculated numerically after measuring the DC level.

II. THE CIRCUIT DESCRIPTION
The measurement circuit's overall design schematic is illustrated in Fig. 2. DDS methodology can be implemented on FPGA to generate the sinusoidal excitation signal [21], [22]. It provides fine frequency resolution, fast frequency switching between output signals, and continuous phase signal generation [20]. In this work, digital implementation of the excitation signal is accomplished by the means of Xilinx's DDS Intellectual Property (IP) [23]. A 12-bit digital-to-analog converter (DAC) is used to convert digitally generated sinusoidal samples into analog domain. In order to make DAC work properly, a DAC driver component is implemented on FPGA using hardware definition language (HDL). A passive LPF is added after the DAC to smooth the generated excitation wave. After lossy capacitance is driven by the smoothened sine wave, TIA converts the flowing current into a voltage value. TIA is simply designed with the help of an op-amp and a resistor. The resistor can be connected between the inverting input and output of the op-amp, whereas the non-inverting input is grounded. In this way, the effect of stray capacitances between the lossy capacitance and the input of the op-amp is greatly reduced [10]. TIA produces an output in the form of voltage that contains the values of unknown capacitance and resistance in addition to the values of feedback resistance and excitation voltage. An analogously realized lock-in detector circuit is able to extract the values of lossy capacitance. Lock-in detector either inverts or directly transfers its input signal to the active LPF depending on the position and frequency of the switches. The switches are controlled by the reference signals. These reference signals are two non-overlapping square waves that are obtained by simply dividing the global clock signal; thus, switch-driving circuit consisting of an analog buffer and an inverter as given in [13] is no longer needed. Moreover, a phase shifter component is written in HDL to arrange the phase shift between the input signal and reference signals. The phase shifter component which is implemented digitally on FPGA removes the need for analog realization of a phase shifter circuit as suggested in [16]. Transistor-transistor logic (TTL) level converter is employed to convert 3.3 V square waves into 5 V so that reference signals will be compatible with driving the switches. Since the active LPF should only pass the low-frequency components of its input signal and suppress unwanted higher frequency harmonics, a secondorder Sallen-Key Butterworth LPF with a low cut-off frequency is designed and implemented. The output of the LPF is measured with the aid of the FPGA's integrated 12bit 1 MSPS analog-to-digital converter (ADC) [24]. To sum up, FPGA performs three tasks: generation and application of analog signals, controlling of the phase shift, and measurement of the DC output. As a result, a complete and flexible mixed-signal lossy capacitance measurement circuit is proposed.

III. THEORETICAL ANALYSIS
The voltage at the output of TIA given in Fig. 1 is the signal that will be demodulated by the lock-in detection circuit. Its expression can be written as in (1) in the frequency domain where Vin and Vout are the input and output voltages of TIA, respectively. Zx is the impedance of the lossy capacitance which is composed of desired capacitance and resistance connected in parallel. Rf is the feedback resistor of TIA and ω is the natural frequency of the input signal. Av(f) represents the open-loop gain of the op-amp which is inversely proportional to frequency. If TIA's usual operation frequency is taken into consideration, the open-loop gain value is much larger than the terms it is compared with in (1)'s denominator; thus, the output voltage expression can be simplified as in (2) ( ).
Equation (2) implies that when a sinusoidal input voltage is applied to the input, TIA produces a sinusoidal output wave with different amplitude and phase, but with the same frequency. The output voltage of TIA has two terms with 90 ° phase shift. Therefore, the first component in (2) can be used to extract the value of unknown resistance while the second component can be used to find the capacitance value of the lossy capacitance.
The lock-in detector's role is to demodulate the output of TIA and extract lossy capacitance's unknown values. Its output signal will be proportional to the real or imaginary part of (2) depending on the phase of the reference signal [25]. Although a commercial analog multiplier is not explicitly used, the switches multiply the input signal with a square wave which has amplitude of 1 V and the same frequency with the input signal. If it is assumed that the lock-in detector's input is a sine wave as in (3) where A, ω, and θ represent the input signal's amplitude, natural frequency, and phase shift with the reference signal, respectively. Two 90 ° phase shifted square waves can be generated as reference signals. The square waves can be approximated as the sum of odd frequency sinusoids as given in (4) and (5): The multiplication of the input signal with the first reference signal in (4) results in the in-phase output as given in (6) (2  ) 21 cos (2  ) cos (2( 1) ) . 21 Similarly, when the input signal is multiplied with the shifted reference signal in (5), the product is the quadraturephase output as given in (7)    (2( 1) ) sin(2 ) . 21 A low-pass filter with a cut-off frequency lower than ω stops the high frequency components and passes only the first terms given in (6) and (7). Therefore, the output of lowpass filter for in-phase and quadrature-phase components can be expressed as in (8) and (9): The output of low-pass filter is a constant DC voltage which depends on the input signal's amplitude, as well as the phase difference between the input and the reference signal. The in-phase and quadrature-phase components are not found simultaneously, but the phase shifter implemented on FPGA shifts the phase. Thus, those components can be determined separately. When the phase shift is 0 °,  component is found, and when the phase shift is 90 °, Q component can be found. Consequently, the unknown resistance and capacitance can be calculated using (2), (8), and (9) by the following expressions: The lossy capacitance's parameters can be found by simply measuring I and Q components at the output of the LPF and entering their values into (10) and (11).

IV. COMPUTER-BASED ANALYSIS
Computer-based analysis is the last step before experimental evaluation of the measurement system. The simulations of the excitation signal and reference signals are observed using Vivado Design Suite. On the other hand, the measurement circuit's performance is simulated using a Simulation Program with Integrated Circuit Emphasis (SPICE) program called as "LTSPICE".

A. Signal Generation Simulations
The excitation signal is constructed digitally using DDS method and implemented on FPGA. The signal is a sine wave with a frequency of 2 kHz and amplitude of 3.3 Vp-p. The output frequency of a DDS system can be defined as in (12) where fclk is the FPGA's system clock which is 100 MHz for the used board. Bθ(n) is the number of bits in the phase accumulator and Δθ is the phase increment value. The phase increment value is calculated and entered into Xilinx's DDS Compiler IP to generate the required output frequency. FPGA's system clock is also exploited to generate reference signals. Reference signals are square waves to close and open switches in lock-in detection, so a frequency divider using counters is enough for the signal generation. The reference signals are routed out through Digilent's Peripheral Module (PMOD) interface. Figure 3 depicts the behavioural simulations of the system clock, the excitation signal, and non-overlapping reference signals in-phase with the excitation input. Fig. 3. Digitally generated excitation signal and reference signals. Figure 3 indicates that all of three waveforms have a period of 500 µs period which corresponds to a frequency of 2 kHz. Sine wave samples are produced for a 12-bit DAC that converts digital samples into analog domain and drives the lossy capacitance circuit.

B. SPICE Simulations
SPICE simulation is a decent way of predicting the realworld performance of a circuit. It enables the designer to choose proper components before actually testing circuits. In this work, SPICE-based circuit simulations are carried out using LTSPICE. Initially, the measurement circuit is analysed in two parts. In the first part, the lossy capacitance is driven by the excitation signal and the performance of TIA is observed. In the second part, analog lock-in detector is constructed using switches, op-amps, and passive circuit elements. Finally, the overall measurement circuit's simulation is performed to observe its eventual behaviour.
The schematic of lossy capacitance and TIA is shown in Fig. 4. A 4.7 kΩ resistance and a 10 nF capacitor forms the lossy capacitance. The op-amp OA1 used in TIA design has the following properties: 1M open-loop voltage gain, 10 MHz gain-bandwidth product, 10 V/µs slew-rate, 25 mA output current limit, 45 ° phase-margin, and 500 MΩ input resistance. A 10 kΩ feedback resistance sets the gain of the TIA. Firstly, an AC analysis is carried out for the frequency range from 10 Hz to 100 MHz. Then, a 2 kHz 3.3 Vp-p sine wave is applied to find out the transient response. The frequency response of the lossy capacitance and TIA is shown in Fig. 5. Although the operation frequency is 2 kHz, gain and phase responses are plotted against a wide frequency range. This provides an insight into how the circuit operates at higher frequencies. The circuit shows a behavior of an inverting amplifier. The output amplitude increases with frequency because the impedance of lossy capacitance decreases. However, when the frequency is high enough, the gain-bandwidth product of the op-amp starts to reduce the gain. Two datatips displayed in Fig. 5 indicate that the gain is around 7.86 dB and phase is -149.5 ° at the operating frequency.  Figure 6 indicates the input and output signals in time domain when the transient analysis is run for ten periods. The datatips on Fig. 6 show that if the input's peak is 1.65 V, then the output's peak voltage is 4.064 V at 2 kHz. Thus, since the output voltage does not saturate at this frequency, it contains information of lossy capacitance. The analog lock-in detector's schematic, which is drawn in LTSPICE, is shown in Fig. 7. The detection circuit is made up of multiplication part and LPF part. The multiplication part is designed using four switches which are controlled by two non-overlapping square-waves. When the switches S2 and S3 are on, the switches S1 and S4 are off and the resistors and op-amp produces a gain of +1. Similarly, if the switches S2 and S3 are off, the switches S1 and S4 turn on and the circuit produces a gain of -1. If the input signal and the reference signal are in-phase, then multiplication circuit generates a full-wave rectified output as shown in Fig. 8. Its output signal's frequency is 4 kHz with a peak voltage of 1 V.
The designed LPF performs to find the average value of the output of multiplication circuit which consists of a DC value plus high frequency components. This LPF is an active filter whose topology is Sallen-Key with a second order Butterworth response. The filter's gain is 0 dB in the passband, while the corner frequency is 40 Hz. The gain is -80 dB at 4 kHz so that harmonics are reduced sufficiently by this LPF. The output of the LPF in time domain is shown in Fig. 9. The settling time is around 25 ms and the steady-state output is approximately 0.635 V, which is compatible with (8).   Eventually, the performance of the overall measurement circuit is simulated and tested by bringing the lossy capacitance, TIA, and lock-in detector altogether in the same LTSPICE schematic. Time domain analyzes are carried out to be able find the values of three different lossy capacitances. In these simulations, the excitation signal is 3.3 Vp-p 2 kHz sine wave and the reference signal is 0 V-5 V square wave. The phase shift is given to the system by adding delays to the reference signals. Three different lossy capacitance values are simulated such that Rx = 4.7 kΩ and Cx = 10 nF, Rx = 10 kΩ, and Cx = 4.7 nF, and Rx = 22 kΩ and Cx = 2.2 nF, respectively. The in-phase (I) and quadrature-phase (Q) components are found for each simulation. Simulated values of Rx and Cx are calculated using (10) and (11). All those values are tabulated in Table  I. Then, certain error analyses are carried out. Relative errors can be defined as in (13) simulated value -real value relative error (%)= 100. real value  The worst case error is simulated due to assess the effect of tolerances of the passive circuit elements used in the overall measurement circuit. Resistors and capacitors employed in TIA, multiplication unit and LPF are assumed to have 1 % and 5 % tolerances, respectively. The worst case error is determined by identifying the most deviation from the simulated values of I and Q, then calculating the new worst values of Rx and Cx and comparing them with the real values as given in (13). On the other hand, the phase error is defined as the error caused by a phase mismatch between the input signal and the reference signal. A 5 % phase mismatch is intentionally created between interested signals and relative errors are calculated again using (13). All types of errors and their values are listed in Table II. The maximum relative error is 0.40 % for resistance simulation and 0.89 % for capacitance simulation when component tolerances are not taken into consideration and no phase mismatch exists. However, the maximum relative error increases to 2.55 % for Rx and 3.41 % for Cx when the component tolerances affect the measurement in the worst way. Table II also proves the significance of accurate phase shift because the maximum relative error may rise to 6.38 % for Rx and 14.77% for Cx even for a 5 % phase mismatch.

V. EXPERIMENTAL ANALYSIS
The experimental set-up is arranged according to the schematic given in Fig. 2. Xilinx ZedBoard FPGA is used for generating the required signals and for measuring the DC output of the lock-in detector. The analog lock-in detector circuit is built on a breadboard. A commercial 3-pole passive LC filter with a 0.3 MHz cut-off frequency is connected before the lossy capacitance to smoothen the excitation signal. Also, the reference signals are converted from 0 V-3.3 V to 0 V-5 V by a level converter. Three AD844 high-speed op-amps are used as a part of TIA, multiplication unit, and LPF. A quad bilateral switch CD4066B is used to multiply the input signal with reference signals coming from the level converter. Since ZedBoard's 12-bit ADC has an analog input range from -0.5 V to +0.5 V in bipolar mode, a resistive voltage divider is placed after the LPF so that the input range of the ADC is not exceeded. The circuit diagram for the DC output measurement is given in Fig. 10. The ZedBoard has an in-built anti-aliasing filter which is used to attenuate higher frequency components. Although the ADC stores its analog inputs as 12-bit digital values, the system monitor enables the user to monitor the averaged values of the measured voltages on PC. In this work, this feature is used to monitor measured inphase and quadrature-phase voltage components. The overall design photo of the experimental setup is given in Fig. 11. In order to emulate lossy capacitance, three different combinations of discrete resistors and capacitors are selected. Nominal values of Rx = 4.7 kΩ and Cx = 10 nF, Rx = 10 kΩ and Cx = 4.7 nF, and Rx = 22 kΩ and Cx = 2.2 nF are tested in the measurement circuit. Real values of the capacitance and resistance are obtained from CHY 41R LCR meter that can measure resistance and capacitance with 0.5 % and 0.7 % accuracy, respectively. Table III demonstrates the real values obtained from LCR meter, the experimentally measured values, and relative errors for each lossy capacitance. The maximum relative error is 1.62 % for the resistance measurement and 6.38 % for the capacitance measurement. Those errors can be associated with the on-resistance of the switches, non-ideal characteristics of the op-amps, and variations in the values of passive components. Although the relative errors are related to the measured values of resistance and capacitance, the obtained relative errors are comparable with that of similar studies in the literature [13], [16]. Compared with the simulationbased relative errors, experimental results indicate higher amounts of relative errors because of the aforementioned reasons. On the other hand, the measurement circuit performs better than phase error simulations in terms of relative errors. Thus, phase-related errors are significantly reduced in the experimental circuit with the help of accurate phase shifts provided by the FPGA. The errors caused by the tolerances of the circuit components can be decreased by employing lower tolerance passive elements in the design of TIA and lock-in detector.

VI. CONCLUSIONS
The purpose of this study is to design, simulate, and experimentally test a lossy capacitance measuring circuit consisting of a digital signal processing platform and analog circuit elements. Firstly, theoretical background of the measuring circuit is laid out. Then, computer-based analysis is carried out to anticipate the real-world behaviour of the overall system, including signal generation simulations and SPICE-based circuit simulations. In simulation environment, three different error analyses are performed to determine the possible sources of errors. It is found out that the tolerances of the passive elements used to construct the measuring circuit can cause considerable amount of error. In the worst case scenario, a maximum error is found to be 2.55 % for resistance measurement and 3.41 % for capacitance measurement. Another major factor that causes measurement errors is identified as the inaccurate phase shift. In fact, it can cause 6.38 % and 14.77 % of maximum relative errors for resistance and capacitance measurements, respectively. In order to reduce the effect of phase mismatch, the excitation signal and reference signals are generated using the same internal clock so that the phase shift between these signals is controlled accurately in digital domain. In this way, analog phase shifter circuit and analog switch-driving circuit, suggested in the literature, are also no longer required. This measurement circuit can measure the final DC output of the system with precision, relieving the need for a separate measurement device. Furthermore, the measurement setup can be utilized for analog multiplier based lock-in detector by generating the reference sine wave using DDS method. A limitation of this measurement setup is that the analog lock-in detection part is built on a breadboard which makes it open to environmental interference. Also, undesired noises can be produced from the analog parts of the circuit, unlike the digital lock-in detectors.