Beniseviciute R, Butkus L, Seinauskas R. Analysis of Physical Level Faults of CMOS Integrated Circuits and Bonds with Higher Levels Faults. ELEKTRON ELEKTROTECH [Internet]. 1998Oct.29 [cited 2024Apr.25];18(5). Available from: https://eejournal.ktu.lt/index.php/elt/article/view/16035