TY - JOUR AU - Bareisa, E. AU - Jusas, V. AU - Motiejunas, K. AU - Seinauskas, R. PY - 2011/03/07 Y2 - 2024/03/29 TI - On Delay Test Generation for Non-scan Sequential Circuits at Functional Level JF - Elektronika ir Elektrotechnika JA - ELEKTRON ELEKTROTECH VL - 109 IS - 3 SE - DO - 10.5755/j01.eee.109.3.173 UR - https://eejournal.ktu.lt/index.php/elt/article/view/173 SP - 67-70 AB - Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection. High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. We investigated the application of tests that are generated at functional level for detection of gate-level transition faults. Based on experimental results, we developed a framework of delay test generation for non-scan sequential circuits. The provided comparison with experimental results of other approaches demonstrates the effectiveness of proposed framework. Bibl. 13, tabl. 4 (in English; abstracts in English and Lithuanian).<p><a href="http://dx.doi.org/10.5755/j01.eee.109.3.173">http://dx.doi.org/10.5755/j01.eee.109.3.173</a></p> ER -