Acceleration of Fault Simulation based on a Separate List of Faults for each Test Pattern

Rimantas Seinauskas, Ramunas Cvirka, Greta Rudzioniene

Abstract


A new fault simulation procedure is suggested. Procedure provides fault detection of individual test patterns at the beginning. In this way, most faults are detected quickly. The remaining faults are analyzed by conventional means in respect of a sequence of test patterns. Creation of individual fault lists of test patterns allows speeding up the fault simulation. Fault simulation acceleration increases with circuit size and test coverage.

DOI: http://dx.doi.org/10.5755/j01.eee.21.3.5774


Keywords


fault simulation, testing, design, hardware

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