Design Considerations of an Amorphous Silicon Demultiplexer

Z. Hafdi

Abstract


This paper deals with the optimization of amorphous silicon gate driver circuits for active matrix array applications. It is based on static and dynamic models for hydrogenated amorphous silicon thin-film transistor operations. The models are extended to investigate amorphous silicon demultiplexer functionality. The proposed circuit is an improvement of an earlier published architecture. The circuit performance is discussed and demonstrated to be more reliable. It is shown that the response of the demultiplexer in terms of charging/discharging time is improved, the feed-through is reduced and the optimization of the circuit response is a reliable trade-off between stability and speed. This may contribute to overcome amorphous silicon technology shortcomings.

DOI: http://dx.doi.org/10.5755/j01.eee.19.8.5397


Keywords


Amorphous silicon; a-Si:H TFT; design optimization; demultiplexer

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