Verification of Initialization Sequences for Sequential Circuits

Authors

  • K. Morkunas Kaunas University of Technology
  • R. Seinauskas Kaunas University of Technology

DOI:

https://doi.org/10.5755/j01.eee.112.6.446

Abstract

This article suggests an approach for verification of initializing sequences. Such sequences were discovered using circuit emulating software prototypes. Software prototypes operate using bivalent logics (0 and 1), while hardware testing employs ternary logic (0, 1 and X). Experimental results show, that validation using ternary logic is too strict, labeling good initializing sequences as bad ones. Experimental results are based on ISCAS'89 benchmark. Ill. 1, bibl. 12, tabl. 3 (in English; abstracts in English and Lithuanian).

http://dx.doi.org/10.5755/j01.eee.112.6.446

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Published

2011-06-08

How to Cite

Morkunas, K., & Seinauskas, R. (2011). Verification of Initialization Sequences for Sequential Circuits. Elektronika Ir Elektrotechnika, 112(6), 61-64. https://doi.org/10.5755/j01.eee.112.6.446

Issue

Vol. 112 No. 6 (2011)

Section

ELECTRONICS

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