FPGA based Improved Hardware Implementation of Booth Wallace Multiplier using Handel C
AbstractApplications requiring intensive arithmetic operations such as multiplication are exponentially increasing than ever before. The state of art FPGAs are the preferred implementation platforms for implementation of multipliers inspite of the speed and area issues. In this paper we present implementation of Booth Wallace Multiplier on Xilinx FPGAs. Our approach employs design at the higher level of abstraction using Handel C which also inculcates parallelism at the algorithmic level. Ill. 4, bibl. 4, tabl. 1 (in English; abstracts in English and Lithuanian).
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