On Delay Test Generation for Non-scan Sequential Circuits at Functional Level

  • E. Bareisa
  • V. Jusas
  • K. Motiejunas
  • R. Seinauskas

Abstract

Sequential circuit testing has been recognized as the most difficult problem in the area of fault detection. High-performance circuits with aggressive timing constraints are usually very susceptible to delay faults. We investigated the application of tests that are generated at functional level for detection of gate-level transition faults. Based on experimental results, we developed a framework of delay test generation for non-scan sequential circuits. The provided comparison with experimental results of other approaches demonstrates the effectiveness of proposed framework. Bibl. 13, tabl. 4 (in English; abstracts in English and Lithuanian).

http://dx.doi.org/10.5755/j01.eee.109.3.173

Section
ELECTRONICS