Analysis of Physical Level Faults of CMOS Integrated Circuits and Bonds with Higher Levels Faults

R. Beniseviciute, L. Butkus, R. Seinauskas

Abstract


CMOS integrated circuits layout and transistors faults and coverage by logic gate stuck-at faults checking tests to transistor circuit in this paper are analyzed. The comparable analysis of physical and logical faults by means of complete test sequence is fulfilled. PSPICE and CADENCE modelling systems were applied for faults simulation.

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Print ISSN: 1392-1215
Online ISSN: 2029-5731