Strategy of CMOS IC Layout Topology Design and Verification

  • R. Beniseviciute Kauno technologijos universitetas
  • A. Lipnickas
  • G. Sadauskas
  • G. Vaitkevicius

Abstract

The paper acquaints with design of layout methodology for non standard logical elements and cells of analog cir-cuits. The authors present algorithms of automated and interactive layout design methods and verification of their electri-cal performances. There is given comparison of electrical performances and parameters of their elements of the circuits that have been designed using the mentioned methods. The design has been carried out by CADENCE system, relying on MIETEC cell library.
Published
2016-08-09
Section
Articles