FPGA Implementation of Range Addressable Activation Function for Lattice-Ladder Neuron

Tomyslav Sledevic, Dalius Navakauskas

Abstract


FPGA implementation of hyperbolic tangent activation function for multilayer perceptron structure seems attractive; however, there is a lack of preliminary results on the choice of memory size particularly, when LUT of the function is stored in dedicated on-chip block RAM. The aim of this investigation was to get insights on the distortions of the selected neuron model output by the evaluation of transfer function RMS error and neuron output signal mean and maximum errors while changing the gain and memory size of the activation function. Thus, the range addressable activation function for the second order normalized lattice-ladder neuron was implemented in Artix-7 FPGA. Various gain and memory constrains were investigated. The increase of LUT memory size and gain yielded smaller error of output signal and nonlinear influence on the transfer function. 2 kB of BRAM is sufficient to achieve tolerable less than 0.4 % maximum error utilizing only 0.36 % of total on-chip block memory.

DOI: http://dx.doi.org/10.5755/j01.eie.22.2.14598


Keywords


Lattice-ladder neuron;, nonlinear activation function; transfer function; high-level synthesis; fixed-point arithmetic; FPGA implementation.

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Print ISSN: 1392-1215
Online ISSN: 2029-5731