Enhanced Hardware Efficient FFT Processor Based On Adaptive Recoding CORDIC

Jianfeng Zhang, Hengzhu Liu, Ting Chen, dongpei liu, Botao Zhang

Abstract


In this paper, we propose an enhanced hardware efficient CORDIC-based FFT processor. As the conventional CORDIC is restricted by the data precision and the times of iterations, Adaptive Recoding CORDIC (ARC) is adopted in our design, the bit error precision (BEP) of which is improved to 14th. Simultaneously, Conflict-free parallel memory access scheme and Rom-free twiddle factor generation scheme are both introduced to improve the performance and reduce the memories to store the twiddle factors. Compared with some latest published FFT processors, synthesized results show the proposed FFT processor reduce the hardware overhead while improving the Signal-to-Noise Ratio (SNR). When the operating frequency is 250MHz, the proposed FFT processor performs radix-4 1024-point FFT every 5.4us.

DOI: http://dx.doi.org/10.5755/j01.eee.19.4.1422


Keywords


Fast Fourier transforms; CORDIC; bit error precision; signal to noise ratio

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Print ISSN: 1392-1215
Online ISSN: 2029-5731