Application of Preselection of Test Subsequences in Sequential Test Generation for Functional Delay Faults

E. Bareisa, V. Jusas, K. Motiejunas, R. Seinauskas, L. Motiejunas

Abstract


Testing of high-performance circuits for timing failures is becoming very important. Testing of non-scan circuits using variable clock speeds requires sophisticated testers and clock control circuitry. Due to these drawbacks, delay fault testing in industry has focussed on at-speed test application in non-scan or partial scan circuits. In the paper, we introduced a new fault model, simplified functional delay fault model, and proposed to use two stages in random test generation process. In the first stage called test subsequences preselection we employed for selection of test subsequences the simplified functional delay fault model. Then in the second stage, we consider only the set of preselected test subsequences and use for fault simulation already the usual functional delay fault model. Experimental results were presented to demonstrate the effectiveness of proposed approach. Ill. 2, bibl. 10, tabl. 3 (in English; abstracts in English and Lithuanian).

DOI: http://dx.doi.org/10.5755/j01.eee.118.2.1179


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Print ISSN: 1392-1215
Online ISSN: 2029-5731