Nanotechnology Problems using VMOS, UMOS

Authors

  • T. Keršys Kaunas University of Technology
  • D. Andriukaitis Kaunas University of Technology
  • R. Anilionis Kaunas University of Technology

Abstract

VMOS, UMOS transistors drain and gate are formed in the groove of “V” or “U” form. Channel area is expanded, therefore VMOS and UMOS structures may be used in power chips. Using VMOS, UMOS 40% more free space is saved than using NMOS technology. Nanostructures dimensions are very small, so it is important to keep pn splice at a right depth, during all semiconductor manufacturing technological process. Analyzing influence of each technological operation on structure formation mathematical simulation with program SUPREM IV is used. VMOS and UMOS technological operation was simulated in micro and nano levels. Ill. 10, bibl. 5 (in English; summaries in English, Russian and Lithuanian).

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Published

2006-07-22

How to Cite

Keršys, T., Andriukaitis, D., & Anilionis, R. (2006). Nanotechnology Problems using VMOS, UMOS. Elektronika Ir Elektrotechnika, 70(6), 79-82. Retrieved from https://eejournal.ktu.lt/index.php/elt/article/view/10697

Issue

Vol. 70 No. 6 (2006)

Section

T 171 MICROELECTRONICS

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