Etching Process Simulation in MOS Nanoscale Structures

  • D. Andriukaitis Kaunas University of Technology
  • R. Anilionis Kaunas University of Technology

Abstract

Problems of etching process, related with MOS transistors separation in LOCOS and SOS technologies were researched. Wafer of Si selection depending on crystallographic planes orientation is the main task. The etching rate along direct direction and lateral encroachment depends on crystallographic planes orientation. Wet etching is simulated with program ACES. Test photo mask with 100 nm holes for wafer etching is used for etching process simulation. The highest etching rate reached in Si with crystallographic planes orientation (110) – 23 nm/s. The biggest lateral etching belongs to substance with crystallographic planes orientation (100), 17 nm/s on both sides together in wet etching process. Ill. 11, bibl. 6 (in English; summaries in English, Russian and Lithuanian).

Published
2006-05-20
How to Cite
Andriukaitis, D., & Anilionis, R. (2006). Etching Process Simulation in MOS Nanoscale Structures. Elektronika Ir Elektrotechnika, 69(5), 5-8. Retrieved from http://eejournal.ktu.lt/index.php/elt/article/view/10665
Section
T 171 MICROELECTRONICS