Synthesizing CMOS Circuits for Speed-Power Product Minimization

  • P. Vijayakumar PSG College of Technology
  • K. Gunavathi PSG College of Technology


We propose an efficient algorithm to optimize Power-Delay product in CMOS logic circuits. The proposed algorithm aims at reducing both power dissipation as well as the delay, which is achieved by retiming and stepwise charging techniques. The retiming technique divides the circuit into stages with latches interposed between them, which decreases the delay. After retiming, stepwise charging technique is employed, where in the supply voltage itself is applied in a series of steps before reaching the maximum supply voltage, which reduces the power dissipation. The algorithm is tested on ISCAS benchmark circuits. Experimental results have shown a reduction of around 80% in power-delay product with small area overhead. Ill. 4, bibl. 14 (in English; summaries in English, Russian and Lithuanian).