Testability Analysis of the VHDL Structure for Fault Coverage Improving
Method of digital device testability analysis, which is represented on the system level (VHDL description) for verification and test synthesis tasks simplification for fault coverage improvement on the given test patterns is offered. Method is based on the topological analysis of circuit, which is represented as RTL blocks and circuit’s further modification by separation of testing and functional procedures for testability improving and testing procedure simplification. Ill. 4, bibl. 12 (in English; summaries in English, Russian and Lithuanian).
Copyright terms are indicated in the Republic of Lithuania Law on Copyright and Related Rights, Articles 4-37.