Design of Novel CMOS DCCII with Reduced Parasitics and its All-Pass Filter Applications

In this paper, a novel translinear loop based, high performance Complementary Metal-Oxide-Semiconductor (CMOS) second-generation differential current conveyor (DCCII) is introduced. By using super source follower transistors, very low equivalent impedances are obtained at input terminals x n and x p . In addition, new voltage-mode (VM) and current-mode (CM) first-order all-pass filters (APFs) are proposed to highlight the performance of the designed CMOS DCCII. The designed CMOS implementation is simulated with HSpice using AMS 0.35 µm real process parameters. It consumes only 1.3 mW power with using ±1.25 V power supply voltages. The simulation results of the proposed CMOS DCII circuit and the experimental results for designed VM APF are in very good agreement with the theoretical ones. DOI: http://dx.doi.org/10.5755/j01.eie.22.6.17222


I. INTRODUCTION
Numerous well-known advantages of current-mode (CM) circuits such as high bandwidth, greater linearity, lowvoltage operation, and wide dynamic range are made them popular in the fields of analog signal processing and integrated circuit design [1]- [5].In the open technical literature excessive number of CM circuits exist that promote solutions to a wide spectrum of applications.For an instance works [6]- [16] and references cited therein can be mentioned.Over the last decades a significant research was performed in order to design high performance, low-voltage low-power CM circuits mainly due to the requirement of efficient portable electronic systems with long battery lifetime [10]- [23].
From internal structure implementation point of view, the current subtractor (CS) with current differencing capability [24], [25] forms one of the most important sub-stages of recently proposed high-performance CM active building blocks (ABBs) such as current differencing transconductance amplifier (CDTA) [6], [7], [21], current differencing buffered amplifier (CDBA) [8], [16], [20], [22], operational transresistance amplifier (OTRA) [3], [17], or second-generation differential current conveyor (DCCII) [11]- [15].Although the DCCII element was the first active component in the open literature combining the simplicity of the conventional CCII [1] with current differencing attribute of the conventional CDBA [8], it has not received as much attention as the CDBA yet and up to now only few integrated circuit implementations are available [11]- [14].In order to show versatility of DCCII and increase its importance for analog signal processing, recently it was used as the main sub-block in a frequency compensation scheme of threestage amplifier [15].It is well-known in analog circuit design that reduction of unwanted parasitic terminal capacitance and resistance values increase the bandwidth of a circuit, because of the product of these two quantities form a dominant pole.In accordance with this theory, within this paper a novel CMOS implementation of a low-voltage and low-power high performance DCCII is proposed.The developed internal structure consists of a class AB input stage based on high performance translinear-loop, a CS stage, and a current mirror stage.Compared to previously published CMOS DCCII implementations [11]- [14], here proposed circuit has very low equivalent input impedances at both input xn and xp ports and high equivalent impedance at the output port z due to the used source followers with local feedback.
The paper is organized as follows: The description of DCCII, its new CMOS implementation, two all-pass filter (APF) examples including non-ideal analysis are presented in Section II.The presented filter circuits employ grounded capacitors for easy integrated circuit (IC) implementation and they are also cascadable.Experimental and simulation results are given in Section III to verify the operation of the voltage-mode (VM) APF.Finally, conclusions are given in Section IV.

A. The DCCII and its New CMOS Implementation
The circuit symbol of the DCCII is given in Fig. 1.The current flowing through z port is the difference of currents flowing into xn and xp ports.The voltage of the highimpedance y port is copied to both xn and xp ports with unity gain.Using standard notation, port relations of an ideal DCCII can be described by the following hybrid matrix: The novel CMOS structure of the proposed DCCII, which is given in Fig. 2, is based on class AB translinear loop input stage formed by transistors M1-M4, while CS and current mirror stages are consist of transistors M11-M17, M19, and M18, M20-M24, respectively.Transistors M6, M7 and M9, M10 have equal currents and both pairs serve as DC current sources for the translinear loop.Transistor pair M2 and M11 forms the source follower with local feedback so-called super source follower (SSF) to obtain very small equivalent resistance at port xn with other SSF pair M4 and M12.Other SSF pairs of transistors M14, M17 and M15, M19 are used to obtain very small equivalent resistance at port xp.Current mirror pairs M21, M18 and M24, M20 are used to obtain the difference current at output port z.
The equivalent resistance seen on port y of class AB input stage is equal to where gmk and rok are transconductance and output resistance of k-th MOS transistor, respectively.The equivalent resistance seen on ports xn and xp are equal to [25]: Finally, the equivalent resistance seen on port z can be calculated simply as 18 hence, from output resistance of transistors M18 and M20.

B. Proposed All-Pass Filter Circuits
As application example for the proposed DCCII, two new first-order APF circuits shown in Fig. 3 are also introduced.Assuming ideal DCCII described by (1) and resistor matching R2 = R3 = 2R1 = 2R, transfer functions (TFs) of presented APFs can be expressed as follows:   out CM in 1 . 1 Phase response of the TFs ( 6) and ( 7) is calculated as: hence, the VM and CM APFs provide phase shifting between 0 (at  = 0) to π (at  = ) and π (at  = 0) to 0 (at  = ), respectively.Moreover, the pole (p) and zero (z) frequencies from TFs can be expressed as Fig. 2. The proposed high performance DCCII.Hence, their sensitivities to passive elements are unity in relative amplitude.The proposed VM APF in Fig. 3(a) has high input impedance and CM circuit in Fig. 3(b) has high output impedance.Hence, both proposed APFs have the advantage of being cascadable, i.e. there will be no need for additional voltage buffer or current follower in case of their connection into a voltage-or current-mode signal processing channel, respectively.

C. Non-Ideal Analysis
Considering the non-idealities caused by the physical implementation of the DCCII, its port relations can be described by the following hybrid matrix:       (11) Here the frequency-dependent non-ideal current gains j(s) and voltage gains j(s) for j = {p, n} are ideally equal to unity.Note that, using a single-pole model, they can be defined as: where αoj and oj are DC current and voltage gains of the DCCII, respectively.The bandwidths 1/j and 1/j depend on the fabrication of the DCCII and on the order of a few Grad/s frequency range in current technologies are ideally equal to infinity.However, at low and medium frequencies i.e., f « (1/(2π))  min{1/j, 1/j}, ( 12) and ( 13 Taking into account non-idealities of the DCCII and reanalysing the behaviour of the proposed APFs in Fig. 3, TFs in ( 6) and ( 7) convert to (14) from which it can be seen that the pole ωp and zero ωz frequencies differ and can be given as:   Note that the effect of non-ideal gains can be minimized by precision design of DCCII, i.e. making current and voltage gains very close to unity.

A. Simulation Results
To verify the theoretical studies, the proposed CMOS DCCII implementation shown in Fig. 2 is simulated with HSpice simulation program using AMS 0.35 µm CMOS real process parameters.The aspect ratios of CMOS transistors are listed in Table I.The supply voltages are VDD = -VSS = 1.25 V and the biasing voltage sources are set to be Vbias = -0.36V, Vb1 = 0.24 V, and Vb2 = -0.39V.  Obtained resistance values for both xn and xp input ports are 30.4Ω.Note that it is significantly lower than in previously introduced CMOS DCCII structures available in [11] [14], which x port resistances are more than 100 Ω.
The resistance value of z port is obtained as 45.9 kΩ, which is sufficiently high.The AC current transfer characteristic is depicted in Fig. 5.The current transfer ratios αp and αn are equal to 0.998 and their bandwidths are 325 MHz.The parasitic capacitance appearing between the high-impedance z output port and ground has a value 10.2 fF.Similarly, the voltage transfer ratios and n are equal to 0.965 and their bandwidths are 330 MHz.The impedance and parasitic capacitance appearing between high-impedance input y port and ground are equal to 84 kΩ and 18 fF, respectively.The power consumption of the DCCII is 1.3 mW.Time-domain analyses of the proposed DCCII are also performed.A 1 MHz sinusoidal input current with amplitude of 200 µA peak-to-peak and a 2 MHz pulse input current with amplitude of 200 µA peak-to-peak are applied to xp and xn ports, respectively.The performed timedomain simulation esults are illustrated in Fig. 6.In order to verify the workability of the proposed VM APF shown in Fig. 3(a), it was simulated using the proposed CMOS DCCII in Fig. 2. Passive element values are chosen as R1 = 1 kΩ, R2 = R3 = 2 kΩ, and C = 500 pF to obtain a phase shift of 90° at pole frequency of fp = 320 kHz.AC simulation results, i.e. ideal and simulated phase and gain responses of the filter are given in Fig. 7.As it can be seen the gain response of the proposed VM APF at fp is unity and there is also no deviation in phase compared to theory.

B. Measurement Results
Secondly, in order to confirm the theoretical results and examine the proposed VM APF circuit in more detail, its behavior has also been verified by experimental measurements.The circuit in Fig. 3(a) with a pole frequency of fp  250 kHz has been designed with resistor values of R1 = 0.5 k, R2 = R3 = 1 k, and capacitor C = 1.3 nF.The DCCII has been realized using two commercially available AD844 ICs of Analog Devices with ±12 V supply voltages [26], as it is shown in Fig. 8.The theoretical and experimental results of the gain and phase responses are depicted in Fig. 9.Note that at high frequencies the deviations in gain and phase characteristics are affected by the poles of voltage and current gains as well as by the external terminal parasitics of the readily available ICs.Moreover, according to datasheets, the passive element tolerances of selected discrete components are 2 % and 5 %, which may also affect the precision of fp.In addition, in order to investigate the phase relationship between input and output signals, input and output signals have been applied to the oscilloscope in X-Y mode.The photograph of the experimental result for Lissajous pattern at the fp is shown in Fig. 10.From the obtained results it can be seen that the proposed solution is in good agreement with the theory.

IV. CONCLUSIONS
In this paper, a new high performance CMOS DCCII is investigated.The proposed circuit has low equivalent input impedances on ports xn and xp and high impedance values on ports y and z.As an application example current-and voltage-mode first-order all-pass filters are presented.These circuits have a grounded capacitor for easy IC implementation.Operation of these circuits is verified by computed simulations via HSpice software and by experiments.
. First-order (a) voltage-mode and (b) current-mode AP filters.

FrequencyFig. 7 .
Fig. 7. Ideal and simulated gain and phase responses of the VM first-order AP filter.

Fig. 10 .
Fig. 10.The photograph of the experimental result for Lissajous pattern at the pole frequency (horizontal and vertical scales are 0.1 V/div.).

TABLE I .
ASPECT RATIOS OF CMOS TRANSISTORS IN THE DCCII.